The paper focuses on the design of the Finite Impulse response Filter (FIR) Filter using VHDL programming language. In the FIR filter design the two input sequence x(n) and h(n) are considered of length M= 4 and N= 4 for both respectively. The output of FIR filter is the convolution of two sequences with the tap length (M + N - 1=7). The design considerations are followed to test many input sequences. The transposed structure is considered for the design of FIR filter to optimize the delay. The design in developed in Xilinx 14.2 software and waveform are simulated in Modelsim 10.1 software. The design is also synthesized on SPARTAN -3E FPGA.
Finite Impulse Response (FIR), Field Programmable Gate Array (FPGA), Very High Speed Integrated Circuit Hardware Description language (VHDL).
Hanny Kumar; Kamal Kumar, Transposed Structure Design of FIR Filter using VHDL, HCTL Open International Journal of Technology Innovations and Research (IJTIR), Volume 19, Issue 1, March 2016, e-ISSN: 2321-1814, ISBN (Print): 978-1-944170-25-7.