This paper presents a novel CMOS based 4T SRAM, it is highly dense and capable for low power application. The Novel 4T SRAM consumes less power and has less leakage current as well as less read and write time. It is capable of storing the bits efficiently. The novel cell size is 26.46% smaller than the conventional six-transistor SRAM cell using same design rules without any performance degradation. The simulation result of 4T SRAM show that there is extensive enhancement in performance of the proposed circuit parameters like delay, power consumption and leakage current. The Novel 4T SRAM has been analysed on Cadence Virtuoso v6.1.5 in 45 nm Technology.
CMOS 4T SRAM, cell delay, Low leakage, low power consumption, 45nm technology.
Puna Kumar Rajak; Dr. S. N. Singh; Amit Kumar Rajak; Sravan Kumar Kankanala, Low Leakage and High Density 4T CMOS SRAM in 45nm Technology, HCTL Open International Journal of Technology Innovations and Research (IJTIR), Volume 15, May 2015, eISSN: 2321-1814, ISBN (Print): 978-1-62951-974-6.