Implementation of Custom Precision Floating Point Arithmetic on FPGAs

Author(s):

Raj Gaurav Mishra; Amit Kumar Shrivastava

Published in:

HCTL Open International Journal of Technology Innovations and Research, ISSN: 2321-1814.

Published on:

31-January-2013

Volume:

Volume 1, January 2013, ISBN: 978-1-62776-012-6.

Copyright Information:

© 2013 by the Authors; Licensed by HCTL Open, India.

License Information:

This article is an open-access article distributed under the terms and conditions of the Creative Commons Attribution 4.0 International License.

Abstract

Floating point arithmetic is a common requirement in signal processing, image processing and real time data acquisition & processing algorithms. Implementation of such algorithms on FPGA requires an efficient implementation of floating point arithmetic core as an initial process. We have presented an empirical result of the implementation of custom-precision floating point numbers on an FPGA processor using the rules of IEEE standards defined for single and double precision floating point numbers. Floating point operations are difficult to implement on FPGAs because of their complexity in calculations and their hardware utilization for such calculations. In this paper, we have described and evaluated the performance of custom-precision, pipelined, floating point arithmetic core for the conversion to and from signed binary numbers. Then, we have assessed the practical implications of using these algorithms on the Xilinx Spartan 3E FPGA boards.


Keywords

Field Programmable Gate Array (FPGA), Floating Point Arithmetic, Custom-Precision Floating Point, Floating Point Conversion.

Cite this Article

Raj Gaurav Mishra and Amit Kumar Shrivastava, Implementation of Custom Precision Floating Point Arithmetic on FPGAs, HCTL Open International Journal of Technology Innovations and Research, Volume 1, January 2013, Pages 10-26, ISSN: 2321-1814, ISBN: 978-1-62776-012-6.

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