Design of a High Speed Adder

Author(s):

Aritra Mitra; Bhavesh Sharma; Nilesh Didwania; Amit Bakshi

Published in:

HCTL Open International Journal of Technology Innovations and Research (IJTIR), eISSN: 2321-1814

Published on:

02-May-2015

Volume:

Volume 14, April 2015, ISBN:978-1-62951-946-3.

Copyright Information:

© 2015 by the Authors; Licensed by HCTL Open, India.

License Information:

This article is an open-access article distributed under the terms and conditions of the Creative Commons Attribution 4.0 International License.

Abstract

In this paper we have compared different addition algorithms such as Ripple Carry Adder, Carry Save Adder, Carry Select Adder, Carry Look Ahead Adder & Kogge Stone Adder for different performance parameters i.e. Area Utilization, Speed of operation and Power Consumption. A high speed Adder is then designed by merging Kogge Stone & Carry Select Algorithms. The circuits have been designed using Verilog HDL & Synthesize using TSMC 180 nm standard cell. The performance parameters are obtained with the help of Cadence Encounter RTL Compiler.


Keywords

Adder, Carry Select Adder, Kogge Stone Adder, Verilog HDL.

Cite this Article

Aritra Mitra; Bhavesh Sharma; Nilesh Didwania; Amit Bakshi, Design of a High Speed Adder, HCTL Open International Journal of Technology Innovations and Research (IJTIR), Volume 14, April 2015, eISSN: 2321-1814, ISBN (Print): 978-1-62951-946-3.

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