Design and Implementation of an Efficient Single Precision Floating Point Multiplier using Vedic Multiplication

Author(s):

Bhavesh Sharma; Amit Bakshi

Published in:

HCTL Open International Journal of Technology Innovations and Research (IJTIR), eISSN: 2321-1814

Published on:

02-May-2015

Volume:

Volume 14, April 2015, ISBN:978-1-62951-946-3.

Copyright Information:

© 2015 by the Authors; Licensed by HCTL Open, India.

License Information:

This article is an open-access article distributed under the terms and conditions of the Creative Commons Attribution 4.0 International License.

Abstract

This paper contains design of a single precision floating point multiplier by modifying the proposed architecture [6] and then comparing the different floating point multiplier architecture for the various performance parameters. The designs are modeled in Verilog HDL and synthesized based on the TSMC 180nm standard cell library. Comparisons are based on the synthesis result obtained by synthesizing all the multiplier using Cadence Encounter RTL Compiler.


Keywords

Floating Point, Floating Point Multiplier, Vedic Multiplication.

Cite this Article

Bhavesh Sharma; Amit Bakshi, Design and Implementation of an Efficient Single Precision Floating Point Multiplier using Vedic Multiplication, HCTL Open International Journal of Technology Innovations and Research (IJTIR), Volume 14, April 2015, eISSN: 2321-1814, ISBN (Print): 978-1-62951-946-3.

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