This paper contains design of a single precision floating point multiplier by modifying the proposed architecture  and then comparing the different floating point multiplier architecture for the various performance parameters. The designs are modeled in Verilog HDL and synthesized based on the TSMC 180nm standard cell library. Comparisons are based on the synthesis result obtained by synthesizing all the multiplier using Cadence Encounter RTL Compiler.
Floating Point, Floating Point Multiplier, Vedic Multiplication.
Bhavesh Sharma; Amit Bakshi, Design and Implementation of an Efficient Single Precision Floating Point Multiplier using Vedic Multiplication, HCTL Open International Journal of Technology Innovations and Research (IJTIR), Volume 14, April 2015, eISSN: 2321-1814, ISBN (Print): 978-1-62951-946-3.