Design and Implementation of Direct Form FIR Filter

Author(s):

Hanny Kumar; Kamal Kumar

Published in:

HCTL Open International Journal of Technology Innovations and Research (IJTIR), e-ISSN: 2321-1814

Published on:

29-February-2016

Volume:

Volume 18, Issue 2, February 2016, ISBN:978-1-944170-16-5.

Copyright Information:

© 2016 by the Authors; Licensed by HCTL Open, India.

License Information:

This article is an open-access article distributed under the terms and conditions of the Creative Commons Attribution 4.0 International License.

Abstract

The research article presents the design of the direct form of the Finite Impulse Response (FIR) filter using VHDL programming language. Multimedia technology and broadband communication demand the low power and high performance design applications in Digital Signal Processing (DSP). The digital filters are most important element of the communication system and DSP. In the paper 7 tap FIR filter is implemented in Xilinx 14.2 software and functionally simulated in Modelsim 10.1 b software. The design of FIR filter of 4 x 4 configurations uses 9 adders and 16 multipliers. The design is also verified on SPARTAN 3E FPGA.


Keywords

Finite Impulse Response (FIR), Field Programmable Gate Array (FPGA), Very High Speed Integrated Circuit Hardware Description language (VHDL).

Cite this Article

Hanny Kumar; Kamal Kumar, Design and Implementation of Direct Form FIR Filter, HCTL Open International Journal of Technology Innovations and Research (IJTIR), Volume 18, Issue 2, February 2016, e-ISSN: 2321-1814, ISBN (Print): 978-1-944170-16-5.

Download Full-Text PDF

It appears you do not have a PDF plugin for this browser. No issues.. you can click here to download this Full-Text PDF file.

Certificate of Contribution

Certificate of Contribution