A Low Power Design Approach for the Implementation of Ternary Logic

Author(s):

Monika Nagaria; Priyanka Goyal

Published in:

HCTL Open International Journal of Technology Innovations and Research (IJTIR), eISSN: 2321-1814

Published on:

02-May-2015

Volume:

Volume 14, April 2015, ISBN:978-1-62951-946-3.

Copyright Information:

© 2015 by the Authors; Licensed by HCTL Open, India.

License Information:

This article is an open-access article distributed under the terms and conditions of the Creative Commons Attribution 4.0 International License.

Abstract

This paper presents the design and simulation of a ternary CMOS SRAM cell. Ternary Logic is a promising alternative to the conventional binary logic as it reduces the number of interconnects which occupy a large area on a VLSI chip and thereby helps in accomplishing simplicity and energy efficiency. The ternary SRAM was created using cross-coupled ternary inverters using PSPICE 9.1. The inverters were optimized for high noise margins and the optimum transistor sizings were presented.


Keywords

Simple Ternary Inverter (STI); Negative Ternary Inverter (NTI); Positive Ternary Inverter (PTI).

Cite this Article

Monika Nagaria; Priyanka Goyal, A Low Power Design Approach for the Implementation of Ternary Logic, HCTL Open International Journal of Technology Innovations and Research (IJTIR), Volume 14, April 2015, eISSN: 2321-1814, ISBN (Print): 978-1-62951-946-3.

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