This paper presents the design and simulation of a ternary CMOS SRAM cell. Ternary Logic is a promising alternative to the conventional binary logic as it reduces the number of interconnects which occupy a large area on a VLSI chip and thereby helps in accomplishing simplicity and energy efficiency. The ternary SRAM was created using cross-coupled ternary inverters using PSPICE 9.1. The inverters were optimized for high noise margins and the optimum transistor sizings were presented.
Simple Ternary Inverter (STI); Negative Ternary Inverter (NTI); Positive Ternary Inverter (PTI).
Monika Nagaria; Priyanka Goyal, A Low Power Design Approach for the Implementation of Ternary Logic, HCTL Open International Journal of Technology Innovations and Research (IJTIR), Volume 14, April 2015, eISSN: 2321-1814, ISBN (Print): 978-1-62951-946-3.